1. Field of the Invention
The present invention relates to comparators, analog-to-digital converters, and digital-to-analog converters, and more particularly, to such circuits implemented in integrated circuits.
2. Description of Related Art
One type of analog-to-digital converter converts an analog input signal to a digital representation in such a manner that each bit of the digital representation is generated substantially at the same time as the other bits. As a consequence, these converters, often referred to as "flash" converters, can convert an analog signal to a digital representation very quickly, typically in one clock cycle in synchronous circuits. One type of flash converter performs the conversion by comparing the analog input signal to each of a plurality of reference voltages and providing a digital output in accordance with the reference voltage which most closely matches the analog input signal. The reference voltages are typically provided by a string of resistors and the comparison is performed by a bank of comparators. Many flash converters can require as many as 2.sup.N resistors and 2.sup.N -1 comparators for N bits of resolution. Because the required number of resistors and comparators and the input capacitance of the A/D converter can grow exponentially for each desired bit of resolution, flash converters have often not been practical for analog-to-digital converters having a relatively high degree of resolution (on the order of 10 bits or more).
To reduce the complexity of high resolution converters, many converters generate the digital output one bit at a time, starting with the most significant bit. The analog value of the first bit is subtracted from the input signal being sampled to produce an analog residue signal. Then, as each subsequent bit is generated, the analog value of the bit is subtracted from the residue. These converters, often referred to as "successive-approximation converters," can require at least one clock cycle for each bit of resolution and are therefore generally much slower than flash converters.
A third converter architecture, usually referred to as a "multi-step converter", combines the approaches of both the flash converter and the successive-approximation converter. The multi-step converter employs a flash converter to produce a first subset of bits which conventionally are the more significant bits of the complete digital representation. These bits, which provide a coarse approximation of the complete digital representation, are then converted by a digital-to-analog converter back to an analog signal which is subtracted from the analog input signal. The resultant residue signal is then converted in a second step to a second subset of digital bits which represent the less significant or fine resolution bits. The complete digital representation of the analog input signal may then be obtained by combining the coarse bits obtained in the first step with the fine bits obtained in the second step. Such an arrangement has the advantage of substantially reducing the overall size of the converter as compared to a single step flash implementation yet is substantially faster than a typical successive-approximation converter.
The process by which the analog equivalent of previously generated digital bits is subtracted from an analog input signal is referred to as "subranging". There are generally two techniques by which subranging is performed. In the direct approach, the bits are converted to an analog voltage signal by a digital-to-analog converter. The analog voltage signal is then subtracted from the analog input signal to produce a residue signal for subsequent conversion. Alternatively, the subtraction is performed indirectly by subtracting an electric charge corresponding to the digital bits from an electric charge corresponding to the input signal. Charge balancing structures typically utilize the indirect technique.
The digital-to-analog converter of a direct type subranging stage may be implemented, in a variety of different circuits. One approach is to use a single resistor string which provides a series of incremental voltages. Switches are operated in response to the digital input to couple the appropriate voltage to the output of the digital-to-analog converter. If the digital-to-analog converter is required to convert a digital representation having a large number of bits, the converter can require a very large number of switches together with a complex logic circuit to provide appropriate clock signals.
Another approach to implement a digital-to-analog converter in a direct type subranging stage, is to use a "current-mode" digital-to-analog converter. In response to a digital word the current mode DAC switches on an appropriate number of current cells. The sum of these currents can be applied across a resistor to create an analog voltage. By applying the analog input signal to the noninverting input of an amplifier and the analog voltage across the resistor (i.e., the output of the current-mode DAC) to the inverting input of the same amplifier, an amplified residue voltage will be created at the output of amplifier. This method requires both a large amount of area as well as power for the higher resolutions. The power requirements can be reduced by increasing the value of the resistor and reducing current of unit cell but such an increase can slow down the DAC.
An indirect type digital to analog converter for a subranging stage may use, in combination with a resistor string, a capacitor array. This technique can reduce the required number of switches but usually requires in addition to the capacitor array, a charge balancing amplifier.
Yet another analog-to-digital converter, known as a "current-mode" converter, typically transforms the analog input signal to an input current using a linear transconductance stage. Each bit of the digital representation to be converted is similarly transformed into separate currents which are subtracted from the input current at a summing junction. In high resolution applications, current-mode digital-to-analog converters generally require a large chip area and power for a large number of current source cells. In addition, highly linear transconductance stages are often difficult to achieve, particularly for wide ranges of input signals.
To reduce the size of the subranging stage of the converter circuit, the digital-to-analog conversion can itself be performed in separate stages. However, because each succeeding stage must typically await the results of the conversion process of the prior stage, the overall speed of the converter circuit is often substantially reduced as a consequence.
A pipeline converter has several stages in which each stage can provide one or more bits of every sample of the input signal. The term "pipeline" refers to the fact that every sample passes through all stages and specific bits of each sample are provided by a specific stage. Furthermore, while one stage is processing a sample of the input signal the next sample is processing the previous sample and so on. Thus, all stages are providing bits at the same time but for different samples of the input signal. Although most existing pipeline analog-to-digital converters deliver the residue of each sample from one stage to the other after subranging, one proposed converter (G. C. Temes, "High Accuracy A/D Converter Configuration, " Electronic Letters, Vol. 21, No. 17, pages 762-763, August, 1985) forwards the sample intact from one stage to the other. This latter converter has the advantage that it does not distort the samples due to imperfections of subranging stages. Nonetheless, creation of reference levels at latter stages for this pipeline architecture can be quite complex.